1. Cross Reference to Related Applications
The present application is related, in part, to U.S. patent application Ser. No. 959,038, High Speed Digital Computer System, filed Nov. 8, 1978 and incorporated herein by reference. The present application is the parent application of divisional U.S. patent applications Ser. No. 91,318 and Ser. No. 91,022, both filed on Nov. 5, 1979.
2. Field of the Invention
This invention relates to architecture for a high speed, compact digital computer system and, more particularly, to circuitry used therein to enhance operating speed and efficiency of such a system.
3. Description of Prior Art
Basic elements of a digital computer include a processor, for processing machine language digital data, and a memory. In general, machine language instructions for controlling processing operations of the processor are stored in memory. Memory may also contain at least portions of data to be processed. Instructions and data are transmitted between processor and memory by processor output and memory output busses. Frequently used sequences of instructions, referred to as microinstruction sequences, are stored in a separate microinstruction memory. Certain instructions, referred to as macroinstructions, cause microinstruction memory to provide a corresponding sequence of microinstructions to the processor. A computer further includes input/output (I/O) apparatus for transmitting instructions and data between computer and external devices. External devices may include, e.g., a control console or a tape storage unit.
Capability of such a digital computer is defined, and limited, by its speed and efficiency in processing data and executing instructions. In general, efficient use of available physical hardware space is required to provide maximum computer capability. Computer system capability and hardware efficiency are particularly important in several areas. Among these areas are computer microinstruction memory; circuitry for selecting successive microinstructions of microinstruction sequences; circuitry for periodically refreshing computer memory; and instruction prefetch circuitry for fetching a next instruction to be executed from computer memory while a current instruction is being executed.
Physical hardware space required by microinstruction memory is determined by the efficiency with which microinstructions are stored therein. Microinstructions organization is determined by computer function while microinstruction memory physical structure is determined by currently available hardware. E.g. a microinstruction set may comprise two or more separate pages of microinstructions; each page containing 256 48-bit microinstructions. Presently available read only memories (ROMs) for storing microinstructions may be structured as 512 word long by 8-bit wide memories. A single page of microinstructions could be implemented with six 512 word by 8-bit ROMs. Storage efficiency, however, would be only 50 percent; microinstruction memory would require twice the physical space required to store an equivalent number of bits.
Another limitation of computer capability is time required to select successive microinstructions of a sequence. Circuitry required for such selection should therefore require minimum hardware implementation, and delay, to provide maximum speed of selection.
The present invention provides computer system improvements which bear upon the above noted computer capability/hardware efficiency factors, thus improving speed and efficiency of operation of the system, and also provides a solution for the aforemention problems and limitations of prior art as will be discussed in detail herein below.